library verilog;
use verilog.vl_types.all;
entity MultSign is
    generic(
        pmi_dataa_width : integer := 8;
        pmi_datab_width : integer := 8;
        module_type     : string  := "Mult"
    );
    port(
        SA              : in     vl_logic_vector;
        SB              : in     vl_logic_vector;
        sproduct        : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_dataa_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_datab_width : constant is 1;
    attribute mti_svvh_generic_type of module_type : constant is 1;
end MultSign;
